关于VHDL块（block）的有关问题
关于VHDL块（block）的问题
在看书的时候看到这样一段代码：
entity guard_examp is
port(I1,I2,CON: in bit;
O1,O2: out bit);
end guard_examp;
architecture Behavioral of guard_examp is
begin
B:block(CON = '1')
begin
O1 <= guarded I1;
O2 <= I2;
end block B;
end Behavioral;
把代码在Xilinx Ise下综合出现这样的错误
error:Line 41. Guarded signal unsupported in block statement.
error:Line 43. Guarded unsupported in signal assignment.
请问为什么会出现这样的问题啊？该如何解决？非常感谢您的回答
------解决思路----------------------
guarder 不能被连线呗
------解决思路----------------------
block and guarded signals can only be used for simulation. Most synthesis tools don't support them. In other words, if you want to make a FPGA image out of it, you are bound to fail.
在看书的时候看到这样一段代码：
entity guard_examp is
port(I1,I2,CON: in bit;
O1,O2: out bit);
end guard_examp;
architecture Behavioral of guard_examp is
begin
B:block(CON = '1')
begin
O1 <= guarded I1;
O2 <= I2;
end block B;
end Behavioral;
把代码在Xilinx Ise下综合出现这样的错误
error:Line 41. Guarded signal unsupported in block statement.
error:Line 43. Guarded unsupported in signal assignment.
请问为什么会出现这样的问题啊？该如何解决？非常感谢您的回答
------解决思路----------------------
guarder 不能被连线呗
------解决思路----------------------
block and guarded signals can only be used for simulation. Most synthesis tools don't support them. In other words, if you want to make a FPGA image out of it, you are bound to fail.