VHDL中的if语句

问题描述：

我对 VHDL 中的 if 语句有疑问，请参阅下面的示例；-)

I've got a question about the if statement in VHDL, see the example bellow;-)

   signal SEQ : bit_vector(5 downto 0); 
signal output: bit; 
    -------

     if(SEQ = "000001") and (CNT_RESULT = "111111") then 
       output<= '1';
      CNT_RESET <= '0';
      else output<='0';
    end if;

我得到:if语句是非法的，并且输出"有多个来源.任何想法

and I get : the if statment is illegal and that "output" has multiply sources. any ideas

答

我认为 if 语句不在进程中?您只能在进程内使用 if 语句.对于流程外的类似功能，您可以使用 when:

I presume the if statement is not inside a process? You can only use if statements inside a process. For similar functionality outside a process, you can use when:

output <= '1' when (SEQ = "000001") and (CNT_RESULT = "111111") else
          '0';

CNT_RESET <= '0' when (SEQ = "000001") and (CNT_RESULT = "111111") else
             '1';

VHDL中的if语句

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