VHDL中顺序和并行的有关问题，为什么顺序逻辑的最终门级电路看起来都是并行的
VHDL中顺序和并行的问题，为什么顺序逻辑的最终门级电路看起来都是并行的？
或者说VHDL中的顺序逻辑只表达了一种依赖的关系？而和指令的按顺序执行还是有区别的？
再或者说，定义在process中的东西是完全可以在process之外来实现的？只不过必须考虑复杂的依赖关系，并且会导致源代码的复杂化？
------解决方案--------------------
VHDL is a hardware description language, and basically it has nothing to do with OO. For sequential logic, the key is clock. Everything has to be synchronized with clock. Since it is a hardware language, eventually it will boil down to logic gate and net list.
C is a totally different beast. It is a programming language, which does not have the concept of synchronous clock. Please do not over-analyze them.
------解决方案--------------------
vhdl始终对应的是硬件
不同于C语言等调试时的单步执行
或者说VHDL中的顺序逻辑只表达了一种依赖的关系？而和指令的按顺序执行还是有区别的？
再或者说，定义在process中的东西是完全可以在process之外来实现的？只不过必须考虑复杂的依赖关系，并且会导致源代码的复杂化？
------解决方案--------------------
VHDL is a hardware description language, and basically it has nothing to do with OO. For sequential logic, the key is clock. Everything has to be synchronized with clock. Since it is a hardware language, eventually it will boil down to logic gate and net list.
C is a totally different beast. It is a programming language, which does not have the concept of synchronous clock. Please do not over-analyze them.
------解决方案--------------------
vhdl始终对应的是硬件
不同于C语言等调试时的单步执行