明日就vhdl考试了，求高手帮忙看看哪错了
明天就vhdl考试了，求高手帮忙看看哪错了
这是我写的一个Moore型状态机
程序报错：Error (10500): VHDL syntax error at p159.vhd(15) near text "="; expecting "(", or "'", or "."
求高手看看怎么错了
------解决方案--------------------
把"="换成"<="
这是我写的一个Moore型状态机
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity p159 is
port(
clk,clr,input:in std_logic;
output:out std_logic_vector(3 downto 0));
end p159;
architecture b of p159 is
type ss is(s0,s1,s2,s3);
signal s:ss;
begin
p1:process(clk,clr)
begin
if clr='0' then s=s0;
elsif clk'event and clk='1' then
case s is
when s0=>if input='0' then s=s1;
end if;
when s1=>if input='1' then s=s2;
end if;
when s2=>if input='1' then s=s3;
end if;
when s3=>if input='0' then s=s0;
end if;
end case;
end if;
end process
p2:process(state)
begin
case s is
when s0=>output<="0010";
when s1=>output<="1001";
when s2=>output<="1100";
when s3=>output<="1110";
end case;
end process;
end b;
程序报错：Error (10500): VHDL syntax error at p159.vhd(15) near text "="; expecting "(", or "'", or "."
求高手看看怎么错了
------解决方案--------------------
把"="换成"<="