VHDL 初学 关于时序有关问题请问

VHDL 初学 关于时序问题请教
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity AD7714Contro is 

port
(
  POL,SYNC,RESET,BUF,STANDBY,CS, SCLK,DOUT: out std_logic;  
  CLK : in std_logic; -- <10MHz
  DRDY,DIN : in std_logic;
  R_set : in std_logic; 
  ADReadData : out std_logic_vector(15 downto 0)
);
end Contro;


architecture Contro of Contro is

constant ComFiltH : std_logic_vector(7 downto 0):= "00100100";
--constant FiltH : std_logic_vector(7 downto 0):= "00000001"; --0x01 50Hz
constant FiltH : std_logic_vector(7 downto 0):= "00000000"; --0x00 200Hz

constant ComFiltL : std_logic_vector(7 downto 0):= "00110100";
--constant FiltL : std_logic_vector(7 downto 0):= "10000000"; --0x80 50Hz
constant FiltL : std_logic_vector(7 downto 0):= "01100000"; --0x60 200Hz

constant ComMode : std_logic_vector(7 downto 0):= "00010100";
constant Mode : std_logic_vector(7 downto 0):= "00100000";
constant ComData : std_logic_vector(7 downto 0):= "01011100";

signal ReadData : std_logic_vector(15 downto 0);
signal OutData : std_logic_vector(7 downto 0);

signal i : std_logic_vector(3 downto 0);
signal j : std_logic_vector(4 downto 0);
signal k : std_logic;
type State is (IntState,FiltHState,WriteFiltH,FiltLState,WriteFiltL,ModeState,WriteMode,WaitState,DataState,ReadState); 
signal ComState : State;

begin
  process(CLK,R_set,DRdy,DIn)  
  begin
  if R_set = '0' then
  RESET <= '0';
  CS <= '1';
  k <= '1';
  i <= "0000";  
  ComState <= IntState;  
  ELSIF (CLK='1' AND CLK'EVENT) THEN  
   
  case ComState is
----------------------
  when IntState =>
  if j > "01000" then
  RESET <= '1';  
  else
  j <= j + 1;
  end if;
  if DRDY = '0' then  
  ComState <= FiltHState; 
  OutData <= ComFiltH;  
  CS <= '0';
  j <= "00000";
  end if;  
   
----------------------FiltHState
  when FiltHState =>
  if (i = "1000") then  
  i <= "0000";
  ComState <= WriteFiltH;
  OutData <= FiltH;  
  elsif (k = '1') then
  DOut <= OutData(7);
  OutData <= OutData(6 DOWNTO 0) & '0';
  k <= '0';
  else
  k <= '1' ;
  i <= i + 1;  
  end if;  
----------------------WriteFiltH
  when WriteFiltH =>