一个vhdl小程序里提示两个error,看不出原因,求教各位前辈,多谢了
一个vhdl小程序里提示两个error,看不出原因,求教各位前辈,谢谢了
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SCNT IS
PORT(CLK,CLR,EN:IN STD_LOGIC;
SEG:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DGT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY SCNT;
ARCHITECTURE SCLK OF SCNT IS
SIGNAL L1,L2,L3,L4:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CLKL:STD_LOGIC;
BEGIN
L1<="0000";L2<="0000";L3<="0000";L4<="0000";
DIV:PROCESS(CLK)
VARIABLE CNTL:INTEGER RANGE 0 TO 500000;
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
IF(CNTL=500000)THEN
CLKL<='1';
CNTL:=0;
ELSE
CLKL<='0';
CNTL:=CNTL+1;
END IF;
END IF;
END PROCESS DIV;
PROCESS(CLK,CLR)
BEGIN
IF(CLR='1')THEN
L1<="0000";L2<="0000";L3<="0000";L4<="0000";END IF;
IF(CLKL'EVENT AND CLKL='1')THEN
IF(EN='1')THEN
IF(L1="1001")THEN
IF(L2="1001")THEN
IF(L3="1001")THEN
IF(L4="1001")THEN
L1<="0000";L2<="0000";L3<="0000";L4<="0000";
ELSE
L1<="0000";L2<="0000";L3<="0000";L4<=L4+'1';END IF;
ELSE L1<="0000";L2<="0000";L3<=L3+'1';END IF;
ELSE L1<="0000";L2<=L2+'1';END IF;
ELSE L1<=L1+'1';END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK)
VARIABLE DGTCNT : INTEGER RANGE 0 TO 3;
BEGIN
IF(DGTCNT=3)THEN
DGTCNT:=0;
ELSE
DGTCNT:=DGTCNT+1;
END IF
IF(DGTCNT=0)THEN
SEG<="1110";
CASE L1 IS
WHEN "0000" => DGT<="00000011";
WHEN "0001" => DGT<="10011111";
WHEN "0010" => DGT<="00100101";
WHEN "0011" => DGT<="00001101";
WHEN "0100" => DGT<="10011001";
WHEN "0101" => DGT<="01001001";
WHEN "0110" => DGT<="01000001";
WHEN "0111" => DGT<="00011111";
WHEN "1000" => DGT<="00000001";
WHEN "1001" => DGT<="00001001";
WHEN OTHERS => DGT<="11111111";
END CASE;
ELSIF(DGTCNT=1)THEN
SEG<="1101";
CASE L2 IS
WHEN "0000" => DGT<="00000011";
WHEN "0001" => DGT<="10011111";
WHEN "0010" => DGT<="00100101";
WHEN "0011" => DGT<="00001101";
WHEN "0100" => DGT<="10011001";
WHEN "0101" => DGT<="01001001";
WHEN "0110" => DGT<="01000001";
WHEN "0111" => DGT<="00011111";
WHEN "1000" => DGT<="00000001";
WHEN "1001" => DGT<="00001001";
WHEN OTHERS => DGT<="11111111";
END CASE;
ELSIF(DGTCNT=2)THEN
SEG<="1011";
CASE L3 IS
WHEN "0000" => DGT<="00000010";
WHEN "0001" => DGT<="10011110";
WHEN "0010" => DGT<="00100100";
WHEN "0011" => DGT<="00001100";
WHEN "0100" => DGT<="10011000";
WHEN "0101" => DGT<="01001000";
WHEN "0110" => DGT<="01000000";
WHEN "0111" => DGT<="00011110";
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SCNT IS
PORT(CLK,CLR,EN:IN STD_LOGIC;
SEG:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DGT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY SCNT;
ARCHITECTURE SCLK OF SCNT IS
SIGNAL L1,L2,L3,L4:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CLKL:STD_LOGIC;
BEGIN
L1<="0000";L2<="0000";L3<="0000";L4<="0000";
DIV:PROCESS(CLK)
VARIABLE CNTL:INTEGER RANGE 0 TO 500000;
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
IF(CNTL=500000)THEN
CLKL<='1';
CNTL:=0;
ELSE
CLKL<='0';
CNTL:=CNTL+1;
END IF;
END IF;
END PROCESS DIV;
PROCESS(CLK,CLR)
BEGIN
IF(CLR='1')THEN
L1<="0000";L2<="0000";L3<="0000";L4<="0000";END IF;
IF(CLKL'EVENT AND CLKL='1')THEN
IF(EN='1')THEN
IF(L1="1001")THEN
IF(L2="1001")THEN
IF(L3="1001")THEN
IF(L4="1001")THEN
L1<="0000";L2<="0000";L3<="0000";L4<="0000";
ELSE
L1<="0000";L2<="0000";L3<="0000";L4<=L4+'1';END IF;
ELSE L1<="0000";L2<="0000";L3<=L3+'1';END IF;
ELSE L1<="0000";L2<=L2+'1';END IF;
ELSE L1<=L1+'1';END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK)
VARIABLE DGTCNT : INTEGER RANGE 0 TO 3;
BEGIN
IF(DGTCNT=3)THEN
DGTCNT:=0;
ELSE
DGTCNT:=DGTCNT+1;
END IF
IF(DGTCNT=0)THEN
SEG<="1110";
CASE L1 IS
WHEN "0000" => DGT<="00000011";
WHEN "0001" => DGT<="10011111";
WHEN "0010" => DGT<="00100101";
WHEN "0011" => DGT<="00001101";
WHEN "0100" => DGT<="10011001";
WHEN "0101" => DGT<="01001001";
WHEN "0110" => DGT<="01000001";
WHEN "0111" => DGT<="00011111";
WHEN "1000" => DGT<="00000001";
WHEN "1001" => DGT<="00001001";
WHEN OTHERS => DGT<="11111111";
END CASE;
ELSIF(DGTCNT=1)THEN
SEG<="1101";
CASE L2 IS
WHEN "0000" => DGT<="00000011";
WHEN "0001" => DGT<="10011111";
WHEN "0010" => DGT<="00100101";
WHEN "0011" => DGT<="00001101";
WHEN "0100" => DGT<="10011001";
WHEN "0101" => DGT<="01001001";
WHEN "0110" => DGT<="01000001";
WHEN "0111" => DGT<="00011111";
WHEN "1000" => DGT<="00000001";
WHEN "1001" => DGT<="00001001";
WHEN OTHERS => DGT<="11111111";
END CASE;
ELSIF(DGTCNT=2)THEN
SEG<="1011";
CASE L3 IS
WHEN "0000" => DGT<="00000010";
WHEN "0001" => DGT<="10011110";
WHEN "0010" => DGT<="00100100";
WHEN "0011" => DGT<="00001100";
WHEN "0100" => DGT<="10011000";
WHEN "0101" => DGT<="01001000";
WHEN "0110" => DGT<="01000000";
WHEN "0111" => DGT<="00011110";