VHDL的有关问题，麻烦看下

architecture behav of EMIF_dsp_fifo is

    signal nARE_delay1,nARE_delay2        :std_logic;
    signal nAWE_delay1,nAWE_delay2        :std_logic;
    
begin
    
process(rst_b,clk)
begin
    if rst_b = '0' then
        nARE_delay1        <= '1';
        nARE_delay2        <= '1';
        
        nAWE_delay2        <= '1';
        nAWE_delay1        <= '1';
    elsif clk'event and clk='1' then
        nARE_delay1        <= nARE;
        nARE_delay2        <= nARE_delay1;
        
        nAWE_delay2        <= nAWE_delay1;
        nAWE_delay1        <= nAWE;
    end if;
end process;

请问下clk上升沿的那两种赋值有什么区别吗？一般什么原因需要这样做？