VHDL四人抢答器代码有异常 麻烦给改下吧 急
VHDL四人抢答器代码有错误 麻烦给改下吧 急急急!
library ieee;
use ieee.std_logic_1164.all;
entity qiangdaqi is
port
(
clk ,rest,allow : in std_logic;
answer : in std_logic_vector(3 downto 0);
stop_lamp,allow_lamp,co,q : out std_logic;
answer_success,answer_foul : out std_logic_vector(3 downto 0)
);
end entity;
architecture rtl of qiangdaqi is
signal alamp : std_logic;
signal foul : std_logic_vector(3 downto 0);
begin
nclk:process (clk,allow) is
begin
if(rest='1')then
q<="0000";
co<='0';
else
if(allow_lamp='1')then
if(clk'event and clk='1') and (answer_success="0000")then
if(q="1111")then
q<="0000";
co<='1';
else
q<=q+'1';
co<='0';
end if;
end if;
end if;
end if;
end process;
lemp_rest_allow:process(rest,allow,co)is
begin
if(rest='1')then
stop_lamp<='1';
allow_lamp<='0'
library ieee;
use ieee.std_logic_1164.all;
entity qiangdaqi is
port
(
clk ,rest,allow : in std_logic;
answer : in std_logic_vector(3 downto 0);
stop_lamp,allow_lamp,co,q : out std_logic;
answer_success,answer_foul : out std_logic_vector(3 downto 0)
);
end entity;
architecture rtl of qiangdaqi is
signal alamp : std_logic;
signal foul : std_logic_vector(3 downto 0);
begin
nclk:process (clk,allow) is
begin
if(rest='1')then
q<="0000";
co<='0';
else
if(allow_lamp='1')then
if(clk'event and clk='1') and (answer_success="0000")then
if(q="1111")then
q<="0000";
co<='1';
else
q<=q+'1';
co<='0';
end if;
end if;
end if;
end if;
end process;
lemp_rest_allow:process(rest,allow,co)is
begin
if(rest='1')then
stop_lamp<='1';
allow_lamp<='0'