使用相同的标签和偏移量位访问和更新2路关联缓存

问题描述:

我对如何在2路关联缓存中访问数据感到困惑。

I am confused on how the data is accessed on a 2-way associative cache.

例如,C = ABS

For example, C = ABS

C = 32KB
A = 2
B = 32bits
S = 256

offset = lg(B) = 5
index = lg(S) = 8
tag = 32 - offset - index = 19

说我有以下地址

tag                    | index    | offset
1000 0000 0000 0000 000|0 0000 000|1 0000
1000 0000 0000 0000 000|0 0000 000|0 0000
1000 0000 0000 0000 000|0 0000 000|1 1010

我的缓存看起来像

index   valid dirty tag      data            valid dirty tag     data
0:      1     0     0x80...   some data1     1     0     0x80... some data2
1:         .                                     .
2:         .                                     .  
3:         .                                     .

如何确定应从两个缓存阵列中的哪一个(数据1与数据2)获取数据当索引和标记位相同时?

How do I determine which of the two cache array I should take the data from (data1 vs data2) when the index and tag bits are the same?

同样,当我需要更新缓存时,如何确定应删除两个数组中的哪些数据

Likewise, how do I determine which of the data in the two array I should kick out when I need to update the cache with the same index and tag bits?

我认为它与偏移位有关,但是我不太确定如何使用偏移位或确切地使用它们代表或映射到缓存数组中。

I am thinking it has to do with the offset bits, but I am not too sure how to use the offset bits or what exactly do they represent or maps to in the cache array.


如何确定哪个两个缓存数组当索引和标记位相同时,我应该从(data1 vs data2)中获取数据?

How do I determine which of the two cache array I should take the data from (data1 vs data2) when the index and tag bits are the same?

缓存进入此状态?具有相同索引和标签的访问将被命中,而不是分配第二个条目。

How could your cache get into this state? An access with the same index and tag would hit instead of allocating a second entry.

在缓存中两次具有相同的物理内存行(具有不同的索引或标签)可以发生是由于由虚拟索引(或标记)引起的同名或同义词问题,但是这种情况

Having the same line of physical memory in cache twice (with different index or tags) can happen because of homonym or synonym problems caused by virtual indexing (or tagging), but this situation is just impossible in a correctly-designed cache.


我该如何确定哪个当我需要使用相同的索引和标记位更新缓存时,应该删除两个数组中的数据吗?

how do I determine which of the data in the two array I should kick out when I need to update the cache with the same index and tag bits?

在这种情况下逐出;

索引选择一组标签。这两个标签(在您的情况下)与地址的标签位匹配。如果有人匹配,那就很成功。

The index selects a set of tags. These 2 tags (in your case) are matched against the tag bits of the address. If one matches, it's a hit. If not, it's a miss.

因此,具有相同索引但不同标签的访问是您需要逐出现有行之一的时候。 通常的替换策略是LRU 。一种实现方法是使集合中的位置重要。每次访问一条线时,其标签就会移到MRU位置。当必须将线从集合中逐出时,LRU位置将被逐出。这将是最近最少访问的行。

So an access with the same index but different tag is when you need to evict one of the existing lines. The usual replacement policy is LRU. One way to implement this is by having the position in the set be significant. Every time a line is accessed, its tag is moved to the MRU position. When a line has to be evicted from the set, the LRU position is evicted. This will be the line that was accessed least recently.

通常,新添加的行位于MRU位置,但是自适应地添加到LRU位置可避免在循环时驱逐有价值的数据在巨大的阵列上。请参阅有关英特尔IvyBridge自适应L3替换策略的博客文章,实验测试以调查硬件行为,并提供一些不错的解释。

Normally newly-added lines go in the MRU position, but adaptively adding into the LRU position avoids evicting valuable data while looping over giant arrays. See this blog post about Intel IvyBridge's adaptive L3 replacement policy for some clever experimental testing to investigate the hardware behaviour, and some nice explanations.


我在想与偏移量位有关

I am thinking it has to do with the offset bits

不是,偏移量位选择一行中的字节。命中/遗失/替换都无关紧要。缓存访问硬件使用偏移量和大小来选择找到右行后要读取或更新的字节范围。

Nope, the offset bits select bytes within a line. hit/miss/replacement doesn't care about this. The cache-access hardware uses the offset and size to select which range of bytes to read or update after the right line is found.