Verilog的位改变位置
假设我有一个寄存器 REG [15：0] my_reg ，它包含一个16位的签署示例：
Assuming I have a register reg [15:0] my_reg, which contains a 16-bit signed sample:
我如何才能找到第一个位变化所在的地方吗？
这意味着，如果假设 my_reg = 16'b0001011011010111 ，我怎么能知道，从 0 第一个变化，以 1 是 my_reg [12] ？同样的开头 1 数，负数，例如 my_reg = 16'b1111011011010111 有兴趣在第一个出现的 0 （这是 11 在这种情况下）。
How can I find the place where the first bit change is located?
Meaning, that if assuming that my_reg = 16'b0001011011010111, how can I know that the first change from 0 to 1 is at my_reg [12]? Same for numbers starting with 1,negative numbers, e.g. my_reg = 16'b1111011011010111 would be interested in the position of the first appearing 0 (which is 11 in this case).
终极目标（添加上下文的一点点）是实现数字FPGA内置自动增益控制（AGC）。
The ultimate goal (to add a little bit of context) is to implement a digital FPGA built-in automatic gain control (AGC).
与上述相同，但参数化技术。使用异或错开一比特，以确定位改变，则使用一个递减的优先连接codeR以输出第一
换地点。我塞满了 my_reg [0] 所以第一位不创建一个增量。
Same technique as described above but parametrized. Use XOR shifted by one bit to determine where bits change, then use a descending priority encoder to output the first
change location. I stuffed with my_reg[0] so the first bit doesn't create a delta.
localparam width=16;
reg [width-1:0] my_reg;
wire [width:0] delta;
reg [$clog2(width)-1:0] index; // Note: $clog2 was added in IEEE1364-2005
integer i;
assign delta = my_reg ^ { my_reg, my_reg[0] };
always @* begin
index = 0;
for (i=0; i<width; i=i+1)
if (delta[i])
index = i;
end
上方EDA操场code（感谢这个抬起头，BTW）
http://www.edaplayground.com/x/3uP